interface charge造句
例句与造句
- interface charge has a profound influence on the breakdown voltage of flr structure . on severe condition it can make the outer flr far from main junction disfunction
界面电荷对场限环终端结构的击穿电压影响很大，严重的甚至可以使远离主结的场限环失去作用。 - the breakdown mechanism of soi ldmos with located charge trenches was analyzed in this thesis . the interface charge model for the breakdown voltage was proposed
本课题分析具有局域电荷槽结构的soildmos的纵向耐压机理，提出界面电荷耐压模型，这是迄今为止所见报道的高压soi器件理想的新模型。 - it was thought that zno buffer layer eliminates the imbalance of interface charge and weaken the thermal stress, so that the dislocation between wide band-gap ii-vi materials and si substrate would be decreased
认为由于zno的存在消除了电荷不匹配以及减少热应力对在si衬底上生长宽带-族半导体材料带来的影响从而减少界面间的缺陷的产生。 - with offset fp structure obtained by using our method the device breakdown voltage is higher than flr structure, and this structure can screen the influence of interface charge in part and improve the stability of device performance
用我们的方法设计的偏移场板结构不仅比场限环结构提高了击穿电压，而且部分地屏蔽了界面电荷对器件击穿电压的影响，提高了器件工作性能的稳定性。 - the distributions of interface charge in the bottom of trenches and electric field in insulation layer were studied for the novel structure . the influences of insulation layer thickness and trench width on breakdown voltage were analyzed and compared with analytical results
利用器件二维数值仿真软件medici，详细研究局域电荷槽内的电荷分布和埋二氧化硅层的电场分布，以及埋二氧化硅厚度和槽宽对耐压的影响。 - It's difficult to find interface charge in a sentence. 用interface charge造句挺难的
- during the high-voltage device design, the thick epitaxial layer ldmos which is compatible with current technology was researched . this device used piecewise vld and multiple region structure f reduce field layer . the using of the f reduce field layer effectively reduce the surface electric field of the device, shorten the length of its drift region, enlarge the choice of range of the ion implant dose of the p layer, and effectively restrain the disadvantageously affection on the breakdown voltage of the interface charge qss
在高压器件研究中对与现有工艺相兼容厚外延ldmos进行研究，该结构采用分段变掺杂多区p~-降场层，有效降低器件的表面电场，缩短器件的漂移区长度，增大p~-降场层注入剂量的选择范围，并有效地抑制界面电荷qss对器件耐压的不利影响。